This invention relates to dual-port random-access-memory circuits, and more particularly, to determining write margins for dual-port random-access memory circuits.
Random-access memory is used in a variety of integrated circuits, such as stand-alone memory chips, programmable logic device integrated circuits, and application-specific integrated circuits. Random-access memory is formed from an array of random-access memory cells. Memory arrays on a programmable logic device typically range in size from a few kilobits to about a megabit or more.
Both single-port and dual-port random-access-memory arrays are used.
Single-port random access memory arrays are accessed using a single port. The single port can be used for read operations or can be used for write operations, but cannot be used for simultaneous read and write operations.
Dual-port random-access memory arrays have two independent ports. If desired, one port can be used for write operations while the other port is used for read operations. The ability to concurrently read and write data allows dual-port random-access-memory arrays to be used in applications such as clock conversion first-in-first-out (FIFO) circuits. In a typical scenario, data is written into a FIFO using one clock signal and is read out of the FIFO using another clock signal.
Single-port memory array circuits are characterized by read and write margin figures of merit. The write margin of a single-port memory array is generally expressed as a voltage. The write margin voltage for a given design is indicative of the tolerance of the design to imperfections due to fabrication variations and operating variations such as changes in temperature and voltage. Designs with large margins are robust. Designs with negative margins are expected to fail.
Because there are numerous possible variations in components and operating conditions for a dual-port memory array, accurate calculation of the read and write margin for the array can be critical. If a logic designer is unable to use read and write margin calculations to evaluate how a given memory design will perform, it will not be possible to properly design a complex memory array.
Conventional methodologies for calculating single-port write margins have been applied to dual-port memory arrays. Unfortunately, write margins that have been calculated in this way have proven to be unreliable. For example, application of conventional single-port margin calculation techniques to a dual-port memory may produce write margin values that are negative, even when the dual-port memory array operates properly.
It would therefore be desirable to be able to calculate write margins satisfactorily for dual-port memory arrays.